Neuro Computing Systems

Research Lab at KTH Stockholm, Sweden

Modular design of a factor-graph-based inference engine on a System-On-Chip (SoC)


Journal article


Indar Sugiarto, J. Conradt
Microprocessors and microsystems, 2018

Semantic Scholar DBLP DOI
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APA   Click to copy
Sugiarto, I., & Conradt, J. (2018). Modular design of a factor-graph-based inference engine on a System-On-Chip (SoC). Microprocessors and Microsystems.


Chicago/Turabian   Click to copy
Sugiarto, Indar, and J. Conradt. “Modular Design of a Factor-Graph-Based Inference Engine on a System-On-Chip (SoC).” Microprocessors and microsystems (2018).


MLA   Click to copy
Sugiarto, Indar, and J. Conradt. “Modular Design of a Factor-Graph-Based Inference Engine on a System-On-Chip (SoC).” Microprocessors and Microsystems, 2018.


BibTeX   Click to copy

@article{indar2018a,
  title = {Modular design of a factor-graph-based inference engine on a System-On-Chip (SoC)},
  year = {2018},
  journal = {Microprocessors and microsystems},
  author = {Sugiarto, Indar and Conradt, J.}
}